Jins Alex ¹, S. Umadevi ¹

Affiliations
1 Department of SENSE, VIT University, Chennai Campus, Chennai - 600 048, Tamil Nadu, IN

Abstract

Background/Objectives: As the size of the chip reduces, nanoscale devices have become more susceptible to manufacturing faults, interference from radiations and transient faults. Many of these errors are not permanent but it causes malfunctioning of circuit either due to the complexity of the circuit or due to the interaction with the software. In this paper, an area and power efficient BIST with self repairing technique has been proposed, which detect and repair the faults in the circuit. Methods/Statistical Analysis: In this research work, a novel Built-In Self-Test (BIST) architecture with self repairing circuit is proposed. The novelty of this architecture is that testing is done along with the self repairing. The Self repairing circuit repairs the fault in the circuit during testing phase itself which increases the reliability of the circuit. Since the insertion of test pattern externally, BIST architecture does not alter the basic multiplier structure. Findings: Average power dissipation of the proposed Built-in self test and self repairing of array multiplier architecture is reduced by 36% since the use of a power efficient test pattern generator. Self repairing has been accomplished by the use of hardware redundancy technique. Also a TMR based self repairing architecture for real time self repairing has been proposed and its area and power dissipation is compared with the other self repairing architecture. Result shows that the BIST with repairing technique is good for low power applications while the TMR based self repairing method is good for real time self repairing applications. The proposed technique can be extended to self repairing processor.

Keywords

Array Multipliers, BIST, DMR, Low Power, TMR

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H. A. Anil Kumar ¹, S. Umadevi ¹

Affiliations
1 School of Electronics Engineering (VLSI Design), VIT Chennai Campus, Chennai - 600127, Tamil Nadu, IN

Abstract

Background: Multiplication is the basic operation in any signal processing systems and financial applications, all these applications requires multiplication to be performed in a faster and efficient manner on a silicon chip. Methods: This paper describes the algorithm and architecture of a BCD parallel multiplier. The design exploits two properties of redundant BCD codes to speed up its computation. Namely, the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition to this, number of new techniques are used in order to reduce significantly latency, area and for implementation on FPGA compared to existing implementations. Findings: Parallel architecture is used for generating partial products using radix-10 recoding technique for signed-digit of a BCD multiplier having set of digits between the range [–5, 5] and a positive set of multiplicand multiples coded in XS-3. Use of this encoding has various advantages like, as XS-3 is a self-complementing code, finding a negative of it is by just complementing the bits of respective number. Also the redundancy in XS-3 code is utilized for generating multiplicand multiples in a simple, faster and a carry-free way. Implemented design has three stages. Partial product generation, reduction and final conversion to BCD. For to implement the design in hardware the partial product reduction architecture is modified here to use a bank of ripple carry adder trees. ODDS representation uses 4-bit binary encoding technique which is similar to non-redundant BCD code, for this reason conventional VLSI circuit techniques such as carry-save adders and compression trees can be used effectively to perform operations on decimal numbers. Conclusion: To show the advantages of the resulted design, RTL model for 8 × 8-digit and 16 × 16-digits multiplication has been synthesized and implemented in Virtex-5 FPGA device. Results shows that the multiplier is about 10–15% delay efficient with existing work and about 14–18% area efficient.

Keywords

Excess-3, FPGA, ODDS, Overloaded BCD, Radix-10 Multiplication

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Sheravi Shivaraj Ramu ¹, S. Umadevi ¹

Affiliations
1 School of Electronics Engineering, VIT University, Chennai Campus, Chennai-600127, Tamil Nadu, IN

Abstract

Objectives: Finite Impulse Response (FIR) filters are widely used in image and signal processing applications and responsible for more total power dissipation. This research work presents modified Distributed Arithmetic (DA)-based approach for realization of low power FIR digital filter. Methods/Statistical Analysis: Power reduction in modified DA-based filter is achieved by turning off the MOS components whenever the input samples of circuit are zero. The proposed filter reduces power consumption by disabling adder operation when inputs are zero. In the conventional DSP applications, it is observed that the average of the zero input sample is very high. Therefore, substantial reduction in power consumption can be obtained by proposed modified DA-based architecture. The proposed DA-based FIR filter is designed using Xilinx® ISE design tool and Cadence® EDA tool. Findings: The proposed work proved that the power reduction is achieved in modified DA-based FIR filter realization when compared with existing LUT-less DA-based architecture of FIR filter. Simulation results shows that proposed architecture can achieve significant power reduction with fewer percentage increases in area and delay for different architectures. For four tap FIR filter 12.5% power reduction is achieved, at the cost of 0.63% extra chip area and 1% increased delay in comparison with conventional DA-based filter architecture. Therefore, the proposed filter can achieve even greater power saving for higher order FIR filters and for more number of zeros in the inputs sample. The proposed technique can also be used for reconfigurable architectures where filter coefficients change during runtime. Conclusion: A low power modified DA-based FIR digital Filter is proposed. Power reduction in proposed design is due to turning off MOS components and is linearly related to number of zeros in input and order of the filter.

Keywords

Distributed Arithmetic (DA), Finite Impulse Response (FIR), Look Up Table (LUT)-based and Look Up Table Less Computing, Low Power, Memory based Computing

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